1. Field of the Invention
The present invention relates generally to semiconductor wafer fabrication and the photolithographic imaging portion thereof. More specifically, the present invention provides for film application methods that compensate for topography of the wafer.
2. Background Art
In the field of semiconductor wafer fabrication, photolithographic imaging on a wafer is highly dependent on the uniformity of the substrate. More specifically, current lithography processes are hindered because across-chip topography typically consumes the entire process depth of focus available in current equipment. Further, often induced by chemical mechanical planarization (CMP) processing, step heights (e.g., distance(s) in a z-direction between high and low point(s) across a chip) can increase in magnitude within an exposure field through each subsequent processing step. These step heights are often observed between static random access memory (SRAM) arrays and random logic and/or between kerf and product. As a result, length scales (e.g., horizontal distance) between regions that are higher and lower than the wafer's nominal height can be on the order of 1 mm. Further, because the chemical vapor deposition (CVD) or spin-on films applied at many levels do not planarize the substrate on a large proportion length scale, the topography is not reduced (i.e., improved) before lithography step(s). Consequently, because the spin-on bottom antireflective coating (BARC) and resist layers also can not planarize a substrate on a range of a millimeter. There are significantly different Z-positions relative to the substrate and no common focal plan at many levels, especially in the back end of line processes (BEOL). Furthermore, with increasingly high numerical aperture (NA), theoretical optical depth of focus is sacrificed for increased resolution, further exacerbating these shortcomings.
Topographical variations across a chip on a wafer can have different characteristic length scales of variation. Planarizing over underlying patterns may be problematic. Consider the example of coating a film on a wafer after performing silicon on insulator (SOI) patterning and etch. At this stage, the wafer might typically have millions of shapes in each die with a small variation in topographical height in between these shapes. In order to improve coating uniformity, one might have to address the magnitude of around 10 perturbations along a 1 micron length as one moves horizontally along the die. Applying a sufficiently thick resist and spin coating can easily planarize a variation of this magnitude and degree.
Contrastingly, where the horizontal distance between peaks and troughs in die (or wafer), topography is greater (i.e., long length scale of variation). An example may be a single die having two areas with SRAM arrays that end up 100 nm higher than surrounding lower density patterning. In this type of scenario, the aforementioned spin coating is ineffective at planarizing the surface of the die because the film essentially starts following the contours of topographical variation rather than simply planarizing the surface, as would be desired.
Currently, various ways to address these shortcomings include either improving the overall process latitude, or fixing CMP rate irregularities that are prone to induce step heights with varying pattern densities. Unfortunately, the aforementioned approaches are both costly and time consuming. In some cases, a solution does not exist and a chip must be redesigned, requiring an entire new reticle set, with complete restart of the product.
In view of the foregoing, there exists a need for methods for providing improved preparation for photolithography that compensates for wafer topography that is both simple, in time and cost, and does not sacrifice throughput.